AR# 52756

14.3 EDK, axi_emc version 1.03a - Possible race condition when AWVALID and ARVALID assert at the same time

描述

There is a possible race condition when AWVALID and ARVALID assert at the same time.

解决方案


This issue appears when two AXI4 MASTERs access the S_AXI_MEM port of the controller version 1.03.a simultaneously.

AssemblyView.JPG
AssemblyView.JPG


A specific sequence of AXI4 accesses to the EMC controller version 1.03a can cause the S_AXI_MEM interface to hang.

The sequence is:

READ_BURST of length 4 (from MASTER1)

followed by:

WRITE (from MASTER0) and READ_BURST (from MASTER1) where AWVALID and ARVALID are asserted at the same time. (Note: WVALID is only one cycle after.)

Following is a snapshot of a simulation that shows S_AXI_MEM hanging. In fact, WREADY and AWREADY never go HIGH, but BVALID pulses HIGH and this is a AXI VIOLATION because BRESP does not flag any error (always 0).

Sim_Bug.JPG
Sim_Bug.JPG


A tactical patch is included at the end of this answer record to apply on the 1.03.a core that comes with the 14.3 release of the tools.




ar52756_EDK_14_3_Preliminary_rev1.zip
AR# 52756
日期 12/03/2012
状态 Active
Type 已知问题
器件
Tools
IP