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AR# 52767

14.3 EDK - TCL errors relating to PS clocks when using the ZC706 import config option in XPS GUI

描述

If I create a BSB project for the ZC706 and use the import ZC706 Development Board Template, the following error occurs in the XPS console window during DRC check:

"Performing System level DRCs on properties...
 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
 ERROR:EDK:3900 - issued from TCL procedure "zynqconfig_do" line 34 processing_system7_0 (processing_system7) - MHS file editing for Zynq related parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
 Value of parameter C_EN_QSPI (1) in MHS conflicts with the setting in Zynq tab. Value of C_EN_QSPI should be 0  
 ERROR:EDK:440 - platgen failed with errors!
 make: *** [implementation/system_axi4lite_0_wrapper.ngc] Error 2
 Done!"

How can I fix this problem?

解决方案

This is a known issue in the XPS standalone flow.

To work around this issue, use the PlanAhead/EDK flow or the Vivado/EDK flow to create the project.

AR# 52767
日期 07/07/2014
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • EDK - 14.3
的页面