We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52789

Serial RapidIO v5.6 - ERROR:MapLib:979 - LUT5 symbol "srio_icon_gen.i_srio_icon/U0/U_ICON/U_TDO........


While implementing Serial Rapid IO v5.6 (Gen 1) core in ISE Design Suite, the following error messages are reported during the map stage:

ERROR:MapLib:979 - LUT5 symbol
_O1) has input signal "srio_icon_gen.i_srio_icon/CONTROL0<3>" which will be
trimmed. See Section 5 of the Map Report File for details about why the input
signal will become undriven.


To resolve this issue, please follow the steps below:

1. Right-click on "Synthesis - XST" in the Processes box,
2. Click on Process Properties
3. Change Property display level to "Advanced"
4. Uncheck the box, "Read Cores"

The issue hereis that the cores are getting wrapped into the synthesis level, when they should be getting pulled in at the NGDBUILD level. Pulling in too early prevents the ChipScope component from getting integrated properly.

Revision History:
11/09/2011 - Initial Release

AR# 52789
日期 11/12/2012
状态 Active
Type 综合文章
  • ISE Design Suite - 14.2
  • RapidIO