描述

This Release Note and Known Issues Answer Record is for the LogiCORE IP Serial RapidIO Gen2 v1.6 which was released in the ISE 14.4 and Vivado 2012.4 design tools and contains the following information:

• New Features
• Supported Devices
• Resolved Issues
• Known Issues
• Other Information

For installation instructions, general CORE Generator tool known issues, and design tool requirements, see the IP Release Notes Guide.

Documentation for this core can be found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_rapidio_do-di-rio-log.htm

解决方案

New Features

ISE Design Suite

• ISE 14.4 design tools support
• Added support for Artix-7 device
• Added support for production parts for Kintex-7 and Virtex-7
• Added support for GES parts for Virtex-7
• Hardware test of Virtex-7 production part
• Hardware test of Artix-7 IES parts

Vivado Design Suite

• 2012.4 tool support
• Added support for Artix-7 device
• Added support for production parts for Kintex-7 and Virtex-7
• Added support for GES parts for Virtex-7
• Support for Vivado Simulator tool
• Hardware test of Virtex-7 production part
• Hardware test of Artix-7 IES parts

Supported Devices

ISE Design Suite

The following device families are supported by the core for this release:

• Virtex-7 devices:
• Virtex-7
• Virtex-7 -2G
• Virtex-7 XT
• Virtex-7 Low Voltage (-2L)
• Kintex-7 devices:
• Kintex-7
• Kintex-7 Low Voltage (-2L)
• Artix-7 devices:
• Artix-7
• Artix-7 Lower Power (-2L)
• Virtex-6 devices:
• Virtex-6 CXT/LXT/SXT/HXT
• Virtex-6 Lower Power (-1L) LXT/SXT

The following device families are supported by the core for this release.

• Virtex-7 devices:
• Virtex-7
• Virtex-7 -2G
• Virtex-7 XT 
• Kintex-7 devices:
• Kintex-7 
• Kintex-7 Low Voltage (-2L)
•   Artix-7 devices:
• Artix-7
• Artix-7 Low Voltage (-2L)

Resolved Issues

ISE Design Suite

• (Xilinx Answer 50831) - Simulation failure under some specific configuration
• (Xilinx Answer 50675) - 7 Series GTX Wrapper Attributes Update
• (Xilinx Answer 50889) - Device ID is set to 8 bits even though 16 bit value is selected in the interface
• (Xilinx Answer 53326) - Reading back the DeviceID always returns 0xFF instead of the value set in the CORE Generator interface

Vivado Design Suite

• (Xilinx Answer 50830) - CRITICALWARNING:[Common 17-54] The object 'port' does not have a property 'IOSTANDARD'
• (Xilinx Answer 50831) - Simulation failure under some specific configuration
• (Xilinx Answer 50675) - 7 Series GTX Wrapper Attributes Update
• (Xilinx Answer 50889) - Device ID is set to 8 bits even though 16-bit value is selected in the interface
• (Xilinx Answer 53326) -  Reading back the DeviceID always returns 0xFF instead of the value set in the CORE Generator interface

Known Issues

ISE Design Suite

• When the ChipScope tool is enabled for the example design, timing might not be met during the implementation process
• (Xilinx Answer 50883) - Implementation might fail with slack violation timing error
• (Xilinx Answer 53542) - Link might train down on 6.25Gbaud x2 and 6.25Gbaud x4 core configurations
• (Xilinx Answer 53937) - phy_link_reset doesn't work
• (Xilinx Answer 55340) - Occasional PNAs seen for x1 configurations running with IDLE2
• (Xilinx Answer 54372) - Support for devices with GTH

Vivado Design Suite

• ChipScope tool support has not been added under the Vivado design tools flow.
• PlanAhead tool is not a supported flow. All development should be done through the Vivado tool.
• Some configurations of the design might not meet timing
• (Xilinx Answer 53542) - Link might train down on 6.25Gbaud x2 and 6.25Gbaud x4 core configurations
• (Xilinx Answer 53937) - phy_link_reset doesn't work
• (Xilinx Answer 55340) - Occasional PNAs seen for x1 configurations running with IDLE2
• (Xilinx Answer 54372) - Support for devices with GTH

• For High Speed transceivers known Issues and answer record list, see (Xilinx Answer 37179).
• For 7-Series FPGA Errata: http://www.xilinx.com/support/documentation/7_series_errata.htm.
• (Xilinx Answer 55341) - The tool generates the same GT Wrapper XCO file for both Kintex-7 and Virtex-7 Devices.
• For LogiCORE IP Serial RapidIO Gen2 v2.0 release notes, see (Xilinx Answer 54648)
• For LogiCORE IP Serial RapidIO Gen2 v1.7 release notes, see (Xilinx Answer 55339)

Revision History

12/18/2012 - Initial release
01/23/2013 - Added (Xilinx Answer 53937)
04/03/2013 - Added (Xilinx Answer 53340)/(Xilinx Answer 54372)