AR# 52934


Can Vivado accept two-dimensional array types as ports?​


When a two-dimensional array is defined as port, my design fails in synthesis with the following error:

ERROR: [Synth 8-2539] port xxx must not be declared to be an array (default settings).


Two-dimensional array types can be accepted as ports by setting the source files type to SystemVerilog.

Right-click the source file and choose Source Node Properties. Then set Type to "SystemVerilog".

AR# 52934
日期 10/13/2016
状态 Active
Type 综合文章
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