We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52993

Vivado Timing - Unconstrained clock network load information seems inconsistent


For unconstrained clock network, load information does not seem consistent to me.


I open a synthesized design,  generate report_clock_network and then open the report. Next to Unconstrained I see "(1 load)".  However, if I right click on Unconstrained and observe loads of the clock directly under the Unconstrained category, the clock show many loads.  How can the number of loads for the clock be more than the total number of unconstrained loads?

Am I reading the report correctly?


The "1 Load" next to the Unconstrained category indicates that there is only one Net that is not constrained.  This net is the "1 load" or 1 item in the Unconstrained category. Looking further down the grouping, the user can see the number of direct loads driven by this clock net.
AR# 52993
日期 08/07/2013
状态 Active
Type 综合文章
  • Vivado Design Suite