AR# 53008


14.x - PAR:WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not completly routed in this design.


I have a design in a Spartan 6 device which it does not generate any Error messages but finishes the PAR stage with the following Warning:

WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not completely routed in this design. See the "<>.unroutes" file for a list of all unrouted signals.
Check for other warnings in your PAR report that might indicate why these nets are unroutable.
These nets can also be evaluated in FPGA Editor by selecting "Unrouted Nets" in the List Window


If there are only a few nets unrouted, it might be possible to route the net manually from FPGA Editor.

In this case, the associated net is a clock signal from a BUFGMUX component.

The design is failing routing in ISE 14.x but has passed in 13.x.

If manual routing does not provide any solution to the problem then an alternative is to use the same placement in 1SE 14.x as was working in ISE 13.x for the BUFGMUX in the design.

Check the location of these components with FPGA Editor in ISE 13.x and use the corresponding constraints:

INST "<>/clkout1_buf" LOC=BUFGMUX_X?Y?;

This will help the routing to complete for the design in ISE 14.x.

AR# 53008
日期 07/31/2014
状态 Active
Type 综合文章
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