The System Control signals (i.e., ERROR and PHY_INIT_DONE) within the MIG Virtex-6 DDR3/DDR2 designs use the LVCMOS25 I/O Standard.
This is not required but is used by default.
As a result, the MIG Virtex-6 tool only allows these pins to be placed in banks that do not contain Data/Address signals.
This ensures incompatible I/O Standards are not LOCed within the same bank.
While the default MIG pin-out flow follows this pin guideline, the Fixed Pin-Out mode incorrectly allows System Control pins to be placed in banks that contain Data or Address signals.
When this happens, Place:864 errors will occur during implementation.