UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53056

7 Series Integrated Block for PCI Express v1.7 - "ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd does not exist"

描述

Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

When generating the 7 Series Integrated Block for PCI Express v1.7 core by selecting VHDL, XST results in the following error:

ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd does not exist
ERROR:Xst:2927 - Source file ../source/PCIe_portion_tandem_cpler.vhd does not exist

解决方案

Tandem configuration support is available only for Verilog for now. Please select 'Verilog' when generating the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
11/26/2012 - Initial release

AR# 53056
日期 06/21/2013
状态 Active
Type 已知问题
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
的页面