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AR# 53114

AXI Bridge for PCI Express v1.05.a - Incorrect UCF constraint generated when using 250 MHz reference clock

描述

Version Found: v1.05.a
Version Resolved and other Known Issues
: See (Xilinx Answer 44969)

When using the AXI PCIe IP with a 250 MHz reference clock, the AXI PCIe IP must be configured with Clock Frequency of REFCLK Input set to 2. However, this creates incorrect UCF constraints as shown below:

"clk250" TNM_NET = "SYSCLK";

Whereas, it should be:

NET 250" TNM_NET = "SYSCLK";

How can I fix this problem?

解决方案

To work around this issue, open the TCL file for the AXI PCIe IP in the EDK install directory:

<XILINX_EDK>\hw\XilinxProcessorIPLib\pcores\axi_pcie_v1_05_a\data\axi_pcie_v2_1_0.tcl

Change line 522 from:

puts $outputFile "\"$ref_clk_sig\" TNM_NET = \"SYSCLK\";"

to:

puts $outputFile "NET \"$ref_clk_sig\" TNM_NET = \"SYSCLK\";"

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
11/29/2012 - Initial release

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AR# 53114
日期 08/26/2013
状态 Active
Type 已知问题
器件
  • Kintex-7
IP
  • AXI PCI Express (PCIe)
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