AR# 53136


MIG 7 Series QDRII+ - A latch is incorrectly inferred when using Synplify and CPT_CLK_CQ_ONLY=TRUE


Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

All users are now required to manually set the top-level RTL parameter CPT_CLK_CQ_ONLY=TRUE to enable a more reliable read data capture scheme; see (Xilinx Answer 53053). However, when Synplify is used a latch is being inferred for the init state machine output "wrcal_en" which causes the wrong write calibration triggers sent to the PHY. The inferred latch causes write calibration failures in hardware.


To work around this issue, a small change to the "qdr_phy_write_init_sm.v" module is necessary whichis included ina drop-in replacement patch attached at the end of this answer record.

To install the patch, extract the contents of "" to the ./user_design/rtl/phy directory of the generated MIG 7 Series design (example: C:\my_ddr_design\user_design\rtl\phy).

Revision History
11/27/2012 - Initial release


文件名 文件大小 File Type 12 KB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
53053 有关 MIG 7 系列 QDRII+ 的设计咨询 - 当出现 CPT_CLK_CQ_ONLY=FALSE 时,会发生读取校准故障 N/A N/A
AR# 53136
日期 03/02/2013
状态 Active
Type 已知问题
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