AR# 53188


2012.x Vivado - SystemVerilog sources are not written to Modelsim .do file for RTL simulation


My Vivado Project contains SystemVerilog sources and I am using Modelsim for simulation.

In the Vivado 2012.x tool I attempted RTL simulation and received errors because the SystemVerilog files are not passed through to the simulators ".do" file.


The Vivado tool is not correctly handling SystemVerilog files when integrating with Modelsim.

To work around this problem with Vivado 2012.x, the ".do" file can be manually edited and run in Modelsim standalone. 

The SystemVerilog files should be passed with the -sv option, for example:

vlog -sv -work work "C:/project/"
vlog -sv -work work "C:/project/"
vlog -sv -work work "C:/project/"

This issue is fixed in the 2013.1 release of Vivado.

AR# 53188
日期 06/11/2014
状态 Archive
Type 已知问题
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