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For the VC7203, when I generate my own IBERT designs as described in Creating the GTX IBERT Core sections of UG846 - VC7203IBERT Getting Started Guide(ISE Design Suite14.3)and UG847 - VC7203 IBERT Getting Started Guide (Vivado Design Suite 2012.3), I see a File Error when opening the IBERT Console in ChipScope tool (as in Figure 1-14 of UG846 and Figure 1-16 of UG847):
Why do I see this error?
This error can be safely ignored.
This error is due to problems with the ChipScope project file (.cpj) that gets generated through the 14.3/2012.3 Board Configuration Settings (BCS) flow (see UG846 Figure 1-19 or UG847 Figure 1-25).
In addition, this issue has been fixed in all of the pre-built 14.3/2012.3 VC7203 IBERT designs, so users downloading these designs from the product page will not observe this error.
This issue will be fixed in 14.4/2012.4.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
52383 | Virtex-7 FPGA VC7203 Characterization Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
AR# 53192 | |
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日期 | 11/30/2012 |
状态 | Active |
Type | 综合文章 |
Boards & Kits |
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