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  3. AR# 53249: MIG 7 Series - Clock input must be connected manually with NO BUFFER option when multiple cores are generated

AR# 53249

MIG 7 Series - Clock input must be connected manually with NO BUFFER option when multiple cores are generated

描述

Version Found: v1.7
Version Resolved: See (Xilinx Answer 45195)

In MIG 7 Series 1.7 and later versions of MIG, when the "NO BUFFER" selection is applied to sys_clk and ref_clk, clocking modifications must be done by the user to connect all clocks properly.

解决方案

If multiple DDR2/DDR3 are generated within the MIG 7 Series GUI with "NO BUFFER" selected for sys_clk or ref_clk, c0_mmcm_clk will be connected to all clock inputs of the PLL in the user design top module.

Users should modify the code manually to set up the expected clocking architecture. If NO BUFFER is selected, no IBUFG or IBUFGDS will be generated. The user should modify the clocking according to (Xilinx Answer 40603).

Revision History
12/3/2012 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40603 MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines N/A N/A
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 53249
日期 09/30/2013
状态 Active
Type 综合文章
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • ISE
  • Vivado Design Suite
IP
  • MIG 7 Series
的页面