AR# 53281

描述

I am attempting to design a video system using the latest Xilinx AXI Video cores and am confused about FSYNC vs. SOF on TUSER for the Video Over AXI Stream protocol that Xilinx now uses for all video IP.

What is Xilinx recommendation for handling frame sync?

解决方案

Xilinx is currently in a transitional period between XSVI (which used fsync) and Video Over AXI4 Stream (which uses SOF on TUSER) interfaces for video. The older cores used XSVI and the new cores now use Video Over AXI4 Stream protocol.

Much of the confusion is around the AXI VDMA because it now adheres to the Video Over AXI4 Stream specification, but it still supports fsync signals (which is legacy).

Following are some recommendations:

• Use a Video Timing Controller core in detect mode on the input.
• Use the Video In to AXI4 Stream core to generate SOF signal from input video timing information.
• Enable SOF on TUSER mode for applicable cores (including the AXI VDMA) and use this for frame synchronization rather than fsync signals. SOF will be propagated through the system automatically by the cores.
• If you have an AXI VDMA in your design:
• set the S2MM side to 'external frame sync' mode and enable 'SOF on TUSER.' Make sure to set the FsyncSrcSelect bit in the S2MM_DMACR register to 2'b10 to select TUSER as the frame sync source
• set the MM2S side to 'free run' mode
• tie off the fsync signals (in XPS, you can leave them unconnected)
• Use a Video Timing Controller core in generate mode on the output to re-generate video timing information.
• Use the AXI4 Stream to Video Out core to synchronize the output video data.

NOTE: If you have an AXI VDMA in your design configured as mentioned above, set the AXI4 Stream to Video Out core in Master timing mode. In this case, synchronization to a VTC generator is achieved through SOF and throttling. If there is no AXI VDMA in the system, set this core in Slave mode.

For more information, see the AXI4-Stream Video IP and System Design Guide (UG934):
http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

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