AR# 53304

描述

As per GES errata (EN183 and EN192), the OOB circuit is enabled by default in 7 series GTX transceivers. 

This errata has been fixed in production silicon. 

Because Aurora 8B10B does not use the OOB circuit, the GTX settings provided in this answer record are required to power down the OOB circuit and to make sure that the downstream circuits ignore the OOB detector outputs.

Aurora 8B10B link initialization will not complete if these attributes are not set.

This issue will not occur with Aurora 8B10B cores targeting 7 series GTX/GTH transceivers in GES silicon.

The attribute settings provided in this answer record should be used for Aurora 8B10B v8.1(ISE 14.1) through v8.3 (ISE 14.4, ISE14.3/Vivado 2012.3) cores targeting 7 series GTX/GTH transceivers in production silicon and Zynq (IES and later silicon) SoC GTX.

解决方案

The following attribute settings should be used for Kintex-7 GTX and Virtex-7 GTX/GTH production silicon, Zynq (IES and later silicon) SoC GTX:

• PCS_RSVD_ATTR[8] = 1'b0
• RXBUF_RESET_ON_EIDLE = FALSE
• RXELECIDLEMODE = 2'b11
• PCS_RSVD_ATTR[8] set to 1'b0 will power down the OOB circuitry.
• RXBUF_RESET_ON_EIDLE set to FALSE does not assert any reset to the Rx buffer in electrical idle condition.
• RXELECIDLEMODE set to 2'b11 will make RXELECIDLE output a static 1'b0.

The above settings are available in the v8.3Rev1 Aurora 8B10B core that was released in the Vivado 2012.4 tools.

Revision History
01/15/2013 - Updated the attribute settings and added Zynq SoC for applicable devices.
12/12/2012 - Initial release

链接问答记录

主要问答记录

相关答复记录