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  3. AR# 53320: Zynq - XPS 14.x - How to interface 7 Series DDRX memory controller by using MIG in PL with PS

AR# 53320

Zynq - XPS 14.x - How to interface 7 Series DDRX memory controller by using MIG in PL with PS

描述

I want to create a design with a 7 series DDRx controller using Memory Interface Generator (MIG) in PL and interface it with the PS section.

解决方案

7 Series DDRX memory controller with MIG in PL interfacing with PS.
 
1. Open EDK XPS 14.3/14.4 tools.
2. Create a new Base System Builder (BSB) project and select AXI Interface.
3. Select Zynq ZC706 Evaluation Platform.
4. Select Next and Finish the BSB wizard.
5. From the IP Catalog, select Memory and Memory Controllers
6. Double click / right click to add an AXI 7 series memory controller (DDRx) to the design. The Xilinx Memory Interface Generator (MIG) window will be launched.

Creating DDR3 design in PL using MIG

1. Launch the MIG wizard through CORE Generator.
2. Select AXI4 interface and click Next to continue.
3. Select DDR3 SDRAM and click Next to continue.
4. Select the  UDIMM, MT8JTF12864HZ-1G6G1 and click Next to continue.
5. Set the internal Termination Impedance to 50.
6. On the Pin/Bank Selection Mode screen, select the Fixed Pin Out I/O's to be used.
7. Validate the UCF by using the MIG tools.
8. Ensure that Below UCF be used if you are configuring the DDR3 memory through MIG.
9. MIG allots a specific bank to the DDR3 memory controller.
10. Correct the UCF as per below for the ZC706 board after creating the system through MIG in PL.

NET "DDR_WEB"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "N23" ;
NET "DDR_VRP"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M21" ;
NET "DDR_VRN"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N21" ;
NET "DDR_RAS_n"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "N24" ;
NET "DDR_ODT"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L23" ;
NET "DDR_DRSTB"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F25" ;
NET "DDR_DQS[3]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "L28" ;
NET "DDR_DQS[2]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "G29" ;
NET "DDR_DQS[1]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C29" ;
NET "DDR_DQS[0]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C26" ;
NET "DDR_DQS_n[3]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "L29" ;
NET "DDR_DQS_n[2]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "F29" ;
NET "DDR_DQS_n[1]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "B29" ;
NET "DDR_DQS_n[0]"   IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "B26" ;
NET "DDR_DQ[9]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A27" ;
NET "DDR_DQ[8]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A29" ;
NET "DDR_DQ[7]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E27" ;
NET "DDR_DQ[6]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D26" ;
NET "DDR_DQ[5]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E26" ;
NET "DDR_DQ[4]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B25" ;
NET "DDR_DQ[3]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D25" ;
NET "DDR_DQ[31]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M30" ;
NET "DDR_DQ[30]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L30" ;
NET "DDR_DQ[2]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B27" ;
NET "DDR_DQ[29]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M29" ;
NET "DDR_DQ[28]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K30" ;
NET "DDR_DQ[27]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J28" ;
NET "DDR_DQ[26]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J30" ;
NET "DDR_DQ[25]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K27" ;
NET "DDR_DQ[24]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J29" ;
NET "DDR_DQ[23]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F30" ;
NET "DDR_DQ[22]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G30" ;
NET "DDR_DQ[21]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F28" ;
NET "DDR_DQ[20]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E30" ;
NET "DDR_DQ[1]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E25" ;
NET "DDR_DQ[19]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E28" ;
NET "DDR_DQ[18]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H28" ;
NET "DDR_DQ[17]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G27" ;
NET "DDR_DQ[16]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H27" ;
NET "DDR_DQ[15]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D29" ;
NET "DDR_DQ[14]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D28" ;
NET "DDR_DQ[13]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D30" ;
NET "DDR_DQ[12]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C28" ;
NET "DDR_DQ[11]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A28" ;
NET "DDR_DQ[10]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A30" ;
NET "DDR_DQ[0]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A25" ;
NET "DDR_DM[3]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K28" ;
NET "DDR_DM[2]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H29" ;
NET "DDR_DM[1]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B30" ;
NET "DDR_DM[0]"   IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C27" ;
NET "DDR_CS_n"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "N22" ;
NET "DDR_CKE"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M22" ;
NET "DDR_Clk"   IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "K25" ;
NET "DDR_Clk_n"   IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "J25" ;
NET "DDR_CAS_n"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M24" ;
NET "DDR_BankAddr[2]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M25" ;
NET "DDR_BankAddr[1]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M26" ;
NET "DDR_BankAddr[0]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M27" ;
NET "DDR_Addr[9]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J23" ;
NET "DDR_Addr[8]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F27" ;
NET "DDR_Addr[7]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K22" ;
NET "DDR_Addr[6]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H26" ;
NET "DDR_Addr[5]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G24" ;
NET "DDR_Addr[4]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J26" ;
NET "DDR_Addr[3]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G25" ;
NET "DDR_Addr[2]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L27" ;
NET "DDR_Addr[1]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K26" ;
NET "DDR_Addr[14]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J24" ;
NET "DDR_Addr[13]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H23" ;
NET "DDR_Addr[12]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K23" ;
NET "DDR_Addr[11]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H24" ;
NET "DDR_Addr[10]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G26" ;
NET "DDR_Addr[0]"   IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L25" ;
 
11. Select the Edit Current EDK IP configuration Tab and click Next.
12. Select Next and Finish.
13. You will see a window of instantiate and IP connect, click OK.
14. Go back to the XPS window and click on the Bus Interfaces Tab and ensure either memory controller is added.
15. Click on Generate Netlist.
16. Click on Generate Bit Stream.
AR# 53320
日期 05/18/2018
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • EDK - 14.3
IP
  • Memory Interface
Boards & Kits
  • Zynq-7000 SoC ZC706 Evaluation Kit
的页面