AR# 53331: LogiCORE IP AXI Video Direct Memory Access v5.03.a - Genlock Source bit in control register not set by driver
LogiCORE IP AXI Video Direct Memory Access v5.03.a - Genlock Source bit in control register not set by driver
I am trying to configure the AXI VDMA using the provided driver. I call the XAxiVdma_GenLockSourceSelect() function to set the genlock source for the MM2S side. In my hardware, I set the MM2S to genlock slave and I am using internal genlock mode, as recommended. However, reading back the MM2S Control Register, the genlock source bit is still set to 0, indicating external genlock. This results in choppy video on the screen. What is going on?
This is a known issue with this version of the driver (driver version v4.01.a). The workaround is to not call the XAxiVdma_GenLockSourceSelect() function and directly write the MM2S control register instead. Simply use the utilities in xil_io.h to mask in the genlock_src bit.
mm2s_cr = Xil_In32(BaseAddress+XAXIVDMA_TX_OFFSET+XAXIVDMA_CR_OFFSET);
Xil_Out32(BaseAddress+XAXIVDMA_TX_OFFSET+XAXIVDMA_CR_OFFSET, mm2s_cr | XAXIVDMA_CR_GENLCK_SRC_MASK);
This will be fixed in the next version of the driver (driver version v4.03.a)