AR# 53350

ISE Simulator: ERROR:HDLCompiler:1654 - Instantiating <(null)> from unknown module <****>

描述

This article explains the cause of errors similar to the below and how to work around them.

Starting static elaboration
ERROR:HDLCompiler:1654 - "C:/Users/ppopescu/Desktop/hydra_PP/mixed_verilog_vhdl_example/sources/encapsulated_mixed_code.v" Line 20: Instantiating <(null)> from unknown module <dff_vhdl>
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

解决方案

This error is normally generated when a VHDL module has not been instantiated properly in the top level Verilog/VHDL file.

As an example refer to the code below:

module example(
    input clk,
    input in,
    output out
    );

wire q1d2;

dff_vhdl
   (
   .clock(clk),
   .data_in(q1d2),
   .data_out(out)
   );

endmodule

You can clearly see that the instance dff_vhdl is not properly declared.

The instance name is missing.

This will generate an Error similar to the following:

You need to correct the code as below and it will run correctly.

module example(
    input clk,
    input in,
    output out
    );

wire q1d2;

dff_vhdl dff_vhdl_instance   (
   .clock(clk),
   .data_in(q1d2),
   .data_out(out)
   );

endmodule

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AR# 53350
日期	07/25/2014
状态	Active
Type	综合文章
Tools	ISE Design Suite - 14

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