Starting static elaboration
ERROR:HDLCompiler:1654
-
"C:/Users/ppopescu/Desktop/hydra_PP/mixed_verilog_vhdl_example/sources/encapsulated_mixed_code.v"
Line 20: Instantiating <(null)> from unknown module
<dff_vhdl>
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
This error is normally generated when a VHDL module has not been instantiated properly in the top level Verilog/VHDL file.
As an example refer to the code below:
wire q1d2;
You can clearly see that the instance dff_vhdl is not properly declared.
The instance name is missing.
This will generate an Error similar to the following:
Starting static elaboration
ERROR:HDLCompiler:1654 - "C:/Users/ppopescu/Desktop/hydra_PP/mixed_verilog_vhdl_example/sources/encapsulated_mixed_code.v" Line 20: Instantiating <(null)> from unknown module <dff_vhdl>
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
You need to correct the code as below and it will run correctly.
AR# 53350 | |
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日期 | 07/25/2014 |
状态 | Active |
Type | 综合文章 |
Tools |