解决方案
The Artix-7 FPGA AC701 Evaluation Kit TRD is developed on the Artix-7 FPGA AC701 Evaluation Kit.
The primary components of the TRD are:
- Xilinx 7 series FPGAs Integrated Block for PCI Express core
- Northwest Logic Packet DMA core
- LogiCORE IP DDR3 SDRAM memory interface generator core
- LogiCORE IP AXI4-Stream Interconnect core
- LogiCORE IP AXI Virtual FIFO Controller core
Additionally, the design uses a PicoBlaze processor core to provide power and FPGA die temperature monitoring capability.
The design also provides 32-bit Linux drivers for the Fedora 16 operating system and a graphical user interface (GUI) to control tests and to monitor status.
Requirements:
Hardware
- AC701 Base Kit
- PC with PCI Express slot (x4 / x8 / x16 PCIe v2.1 compliant)
- Keyboard & Mouse
Software
- ModelSim (version specific, see specific TRD version information below)
- Vivado (version specific, see specific TRD version information below)
Note: Before running any command line scripts, refer to the Xilinx Design Tools: Installation and Licensing document to learn how to set the appropriate environment variables for your operating system.
All scripts mentioned in this readme file assume that the XILINX environment variable has been set.
Artix-7 Base Targeted Reference Design v1.0 for Vivado 2012.4 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon.
IP
- 7 series PCIe (pcie_7x) : v1.8
- 7 series MIG (mig_7x) : v1.8.a
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v1.1
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : P.49a
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Artix-7 Base Targeted Reference Design v1.1 for Vivado 2013.1 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon.
IP
- 7 series PCIe (pcie_7x) : v2.0
- 7 series MIG (mig_7x) : v1.9.a
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : P.49a
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.1b
Vivado Design Suite 2013.1
Artix-7 Base Targeted Reference Design v1.2 for Vivado Design Suite 2013.2 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon
IP
- 7 series PCIe (pcie_7x) : v2.1
- 7 series MIG (mig_7x) : v2.0
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : P.49a
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.2a
Vivado Design Suite 2013.2
Artix-7 Base Targeted Reference Design v1.3 for Vivado Design Suite 2013.3 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon
IP
- 7 series PCIe (pcie_7x) : v2.2
- 7 series MIG (mig_7x) : v2.0
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : v2.0
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.2a
Vivado Design Suite 2013.3
Artix-7 Base Targeted Reference Design v1.4 for Vivado Design Suite 2013.4 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon
IP
- 7 series PCIe (pcie_7x) : v3.0
- 7 series MIG (mig_7x) : v2.0
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : v2.0
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.2a
Vivado Design Suite 2013.4
Artix-7 Base Targeted Reference Design v1.5 for Vivado Design Suite 2014.1 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon
IP
- 7 series PCIe (pcie_7x) : v3.0
- 7 series MIG (mig_7x) : v2.0
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : v2.0
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.2a
Vivado Design Suite 2014.1
Artix-7 Base Targeted Reference Design v1.6 for Vivado Design Suite 2014.3 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon
IP
- 7 series PCIe (pcie_7x) : v3.0
- 7 series MIG (mig_7x) : v2.0
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : v2.0
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.2a
Vivado Design Suite 2014.3
Artix-7 Base Targeted Reference Design v1.7 for Vivado Design Suite 2015.1 with Production Silicon
Silicon
- The Artix-7 FPGA AC701 Evaluation Kit ships with Production silicon
IP
- 7 series PCIe (pcie_7x) : v3.1
- 7 series MIG (mig_7x) : v2.3
- AXI Stream Interconnect (axis_ic) : v1.1
- AXI Virtual FIFO Controller (axi_vfifo) : v2.0
- DMA Back End AXI Model (dma_back_end_axi_model) : P.40xd
- LogiCORE IP AXI4-Lite IPIF (axi_lite_ipif) : v1.00.a
- LogiCORE IP AXI Virtual FIFO Controller (axi_vfifo_ctrl_ip) : v2.0
Known Issues
| (Xilinx Answer 53489) |
Artix-7 FPGA AC701 Evaluation Kit - Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 55925) |
Artix-7 FPGA AC701 Evaluation Kit - Recommended machines for Artix-7 FPGA Base Targeted Reference Design |
Software
- QuestaSim v10.3d
Vivado Design Suite 2015.1