[Synth 8-3493] module 'async_fifo' declared at 'C:/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v8_1/ramfifo/async_fifo.vhd:91' does not have matching formal port for component port 'clk' ["C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":118]
[Synth 8-3493] module 'async_fifo' declared at 'C:/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v8_1/ramfifo/async_fifo.vhd:91' does not have matching formal port for component port 'rst' [C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":118]
[Synth 8-3493] module 'async_fifo' declared at 'C:/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v8_1/ramfifo/async_fifo.vhd:91' does not have matching formal port for component port 'wr_en' [C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":118]
[Synth 8-3493] module 'async_fifo' declared at 'C:/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v8_1/ramfifo/async_fifo.vhd:91' does not have matching formal port for component port 'rd_en' ["C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":118]
[Synth 8-3493] module 'async_fifo' declared at 'C:/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v8_1/ramfifo/async_fifo.vhd:91' does not have matching formal port for component port 'din' ["C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":118]
[Synth 8-3493] module 'async_fifo' declared at 'C:/Xilinx/14.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v8_1/ramfifo/async_fifo.vhd:91' does not have matching formal port for component port 'dout' ["C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":118]
[Synth 8-285] failed synthesizing module 'async_fifo_exdes' ["C:/my_project/project_1/project_1.srcs/sources_1/imports/example_design/async_fifo_exdes.vhd":89]
This issue occurs when the following conditions are all true:
Vivado is finding the HDL file delivered with the ISE DS installation that has not been customized to match any user parameters and contains all available ports.
Possible workarounds are as follows:
This issue has been fixed in Vivado release 2013.2.