Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 45195)
A number of timing paths within the MIG PHY are not being timed and will appear in the "unconstrained_endpoints" section of the report_timing_summary and check_timing reports:
RLDRAMII/3 example:
Checking 'no_clock'.
There are 18 register/latch pins with no clock driven by: u_mig_rldram/u_mig_7series_v1_7_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/PHASER_IN_inst.phaser_in/ICLK and possible clock pin by: rldiii_qk_n[3] rldiii_qk_p[3]
There are 10 register/latch pins with no clock driven by: u_mig_rldram/u_mig_7series_v1_7_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/PHASER_IN_inst.phaser_in/ICLKDIV and possible clock pin by: rldiii_qk_n[3] rldiii_qk_p[3]
There is 1 register/latch pin with no clock driven by: u_mig_rldram/u_mig_7series_v1_7_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/PHASER_IN_inst.phaser_in/PHASEREFCLK and possible clock pin by: rldiii_qk_n[3] rldiii_qk_p[3]
...
There are 3 register/latch pins with constant_clock.
Checking 'unconstrained_endpoints'.
There are 264 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
QDRII+ example:
Checking 'no_clock'.
There is 1 register/latch pin with no clock driven by: u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/incr_addr_reg_i_2/O and possible clock pin by: u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[0]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[10]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[11]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[12]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[13]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[14]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[1]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[2]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[3]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[4]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[5]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[6]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[7]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[8]/Q u_mig_qdr/u_mig_7series_v1_7_qdr_phy_top/u_qdr_phy_write_top/u_qdr_phy_write_init_sm/phy_init_cs_reg[9]/Q
...
There are 3 register/latch pins with constant_clock.
Checking 'unconstrained_endpoints'.
There are 268 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
These unconstrained_endpoints are a result of the Vivado timing tools not being able to propagate a clock to the ICLK/ICLKDIV output pins of the PHASER_IN.
Because these clocks are derived from the PHASERREFCLK, which is driven by CQ_P for QDRII+ designs and QK_P for RLDRAMII/3 designs, these clocks must be defined in the XDC constraint file.
In order for the Vivado timing tools to properly analyze these paths, the following XDC constraint must be used:
QDRII+:
create_clock -period 2.500 -name phaserrefclk_phaser_in -waveform {0.000 1.2500} [get_ports {qdriip_cq_p[0]}]
create_clock -period 2.500 -name phaserrefclk_phaser_in -waveform {0.000 1.2500} [get_ports {qdriip_cq_p[1]}]
...
RLDRAMII/3:
create_clock -period 2.500 -name phaserrefclk_phaser_in -waveform {0.000 1.2500} [get_ports {qdriip_qk_p[0]}]
create_clock -period 2.500 -name phaserrefclk_phaser_in -waveform {0.000 1.2500} [get_ports {qdriip_qk_p[1]}]
...
Note: Adjust the period and hold time requirements accordingly to match your system.
Revision History
12/10/2012 - Initial release
| AR# 53375 | |
|---|---|
| 日期 | 01/26/2015 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| Tools | |
| IP | |