If implementing the MIG 7 Series DDR3 v1.7 design, timing violations might be seen in the OCLKDELAY calibration module. This answer record details why these violations occur and indicates the work-around.
These timing violations are due to many levels of logic in the OCAL_NEW_DQS_WAIT state. These levels of logic are reduced in the MIG 7 Series v1.8 OCLKDELAY calibration module. If timing violations occur, please update to the new rtl.