AR# 53434

MIG 7 Series DDR3 - Potential timing violations in OCLKDELAY calibration

描述

Version Found: 1.7
Version Resolved: See (Xilinx Answer 45195)

If implementing the MIG 7 Series DDR3 v1.7 design, timing violations might be seen in the OCLKDELAY calibration module. This answer record details why these violations occur and indicates the work-around.

解决方案

These timing violations are due to many levels of logic in the OCAL_NEW_DQS_WAIT state. These levels of logic are reduced in the MIG 7 Series v1.8 OCLKDELAY calibration module. If timing violations occur, please update to the new rtl.
AR# 53434
日期 01/31/2013
状态 Active
Type 已知问题
器件
IP