AR# 53437


MIG 7 Series RLDRAM II - bit width mismatch for vio_fixed_bl_value causes simulation errors


Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 45195)

When simulating the MIG 7 Series RLDRAM II design, the following simulation errors can be seen:

# sim_tb_top.COMP_INST[0].CIO_MEM.memory_write: at time 74249163.0 ps ERROR: Memory overflow. Write to Address 000200 with Data xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx040000000400000004 will be lost.
# You must increase the MEM_BITS parameter or define MAX_MEM.
# Break in Task memory_write at rldram2_cio_model.v line 434


This simulation error can occur as a result of a bit width mismatch of thevio_fixed_bl_value signal in the mig_7series_v1_#_traffic_gen_top.v module. In themig_7series_v1_#_traffic_gen_topmodule, vio_fixed_bl_value is 10 bits while in example_top.v it is 8 bits.

To work around the error,vio_fixed_bl_value needs to be concatenated with 2b'0 and passed tomig_7series_v1_#_traffic_gen_top in example_top.v as follows:

(.vio_fixed_bl_value ({2'b00, vio_fixed_bl_value}),

Revision History
12/18/2012 - Initial release



Answer Number 问答标题 问题版本 已解决问题的版本
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 53437
日期 02/07/2013
状态 Active
Type 已知问题
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