AR# 53511

AXI Bridge for PCI Express v1.05.a [Vivado 2012.3] - [IP_Flow 19_1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0'

描述

Version Found: v1.05.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When generating AXI Bridge for PCI Express v1.05.a core in Vivado Design Suite 2012.3, the tool gives the following error message:

[IP_FLOW 19-167] Failed to deliver one or more file(s).
[IP_FLOW 19-1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0'.
[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate 'Verilog Synthesis' output product for IP 'axi_pcie_v1_05_a_0'':

解决方案

This is a known issue to be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
12/17/2012 - Initial release

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Answer Number	问答标题	问题版本	已解决问题的版本
44969	AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7	N/A	N/A

AR# 53511
日期	08/26/2013
状态	Active
Type	综合文章
Tools	EDK Vivado Design Suite
IP	AXI PCI Express (PCIe)

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AR# 53511

AXI Bridge for PCI Express v1.05.a [Vivado 2012.3] - [IP_Flow 19_1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0'

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