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AR# 536

Error in simulation of carry logic : cy4 symbol : incorrect delay attributes : hold time violation

解决方案




PROGRAM: Viewdraw Libraries

VERSION: 5.1 (LIBVER 2.0.0)

PLATFORM(s): ALL

SHORT DESCRIPTION: The CY4 symbol has the A0 input delay annotated to the B0
input and the B0 input delay is lost.

PROBLEM: This problem causes timing simulation to be incorrect in
unpredictable ways. If the routing delay to A0 is greater
than the delay to B0, the path through B0 will appear to be
slower than it really is. If the delays are the reverse, the
path through B0 will appear FASTER than it really is.

CAUSE: The XC4000 CY4 model contains a BUF element at the B0 input
($1I161) which contains the following parameters:

TPLH=@A0DLY1
TPHL=@A0DLY0

Of course, these are the parameters for the A0 input (and they are on
the A0 BUF as well). They should be:

TPLH=@B0DLY1
TPHL=@B0DLY0


SOLUTION: You can push into the CY4 schematic, modify the attributes,
and then write a local copy of it.
This solution only works with the unified library that is
shipped with XACT 5.1.

AR# 536
创建日期 08/31/2007
Last Updated 03/31/1997
状态 Archive
Type ??????