You typically would not need to issue two flush instructions back-to-back, so as long as they do not program the peripherals to expect two separate flush requests when there is two flush instructions being issued, there is NO issue.
If there are other DMA peripheral request instructions in between, then there will be two separate flushes.
The DMARMB and DMAWMB will not work around this issue.
IMPORTANT: DO NOT develop the peripheral core expecting two consecutive separate flushes.
| AR# 53643 | |
|---|---|
| 日期 | 05/21/2013 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 |
|