2. 技术支持
  3. AR# 5364: 1.5i XC4000X* PAR - Express designs with non-RLOC'd carry chains and Coregen modules may not place.
  4. AR# 53643: Zynq-7000 SoC PS-DMA Controller - Any DMAFLUSHP that is executed while there is already a flush in progress is merged and ignored

AR# 53643

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Zynq-7000 SoC PS-DMA Controller - Any DMAFLUSHP that is executed while there is already a flush in progress is merged and ignored

描述

If the DMAFLUSHP is issued twice close together, there is a chance that the Peripheral Request Interface only recognizes one flush request.

解决方案

You typically would not need to issue two flush instructions back-to-back, so as long as they do not program the peripherals to expect two separate flush requests when there is two flush instructions being issued, there is NO issue.

If there are other DMA peripheral request instructions in between, then there will be two separate flushes.

The DMARMB and DMAWMB will not work around this issue.

IMPORTANT: DO NOT develop the peripheral core expecting two consecutive separate flushes.

AR# 53643
日期 05/21/2013
状态 Active
Type 已知问题
器件
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