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AR# 53811

MIG 7 Series RLDRAM 3 - Can an x18 interface fit into a single bank?


Is it possible to fit an x18 RLDRAM3 interface into a single bank when generating the interface through MIG?


Yes, it is possible to fit an x18 interface in a single bank. However, the feasibility of a single bank x18 solution depends on the density of the RLDRAM3 component (i.e., number of address pins), implementation of available pin reductions options (noted below), and possibly the target data rate. The following implementation options should be considered to reduce the interface pin-count and determine if the x18 interface can be placed in a single bank:
  1. Use Internal Vref which allows the Vref pins to be used as normal I/O pins freeing up two pins per bank where inputs are utilized.
    Note: Internal Vref is only an option for data rates below 800 Mb/s. For details, see (Xilinx Answer 42036).
  2. Disable Data Mask (DM); Data Mask can be disabled through the 7 Series MIG tool for designs not requiring the ability to mask data. This saves one I/O pin per data byte group (two I/O pins for an x18 interface).
  3. Use DCI Cascade to free up two I/O pins (VRN/VRP). Note that the VRN/VRP pins are not within the T* byte groups. Data group signals CANNOT be placed on VRN/VRP. RESET _N can ALWAYS be placed on an available VRN/VRP signal. The remaining Address/Control signals are ONLY allowed on VRN/VRP when ALL of the following conditions are met. Please refer to the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide (UG586) for full details.
    • DCI cascade is used.
    • The adjacent byte group (T0/T3) is used as an address/control byte group.
    • An unused pin exists in the adjacent byte group (T0/T3) or the CK output is contained in the adjacent byte group.
  4. VRN and VRP signals (or the non-byte group signals in, for example, HR column banks) are the top and bottom signals within a bank. To utilize both VRN and VRP for address/control, place the Address/Control byte groups on T0 and T3 within the bank. This places one address/control byte group adjacent to VRN and the other adjacent to VRP.
  5. Drive the input sys_clk pair from a different bank within the same I/O column. For full Clocking Guidelines, see (Xilinx Answer 40603).



Answer Number 问答标题 问题版本 已解决问题的版本
40603 MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines N/A N/A
42036 MIG 7 系列 - 内部/外部 VREF 指南 N/A N/A
AR# 53811
日期 10/17/2013
状态 Active
Type 综合文章
  • Virtex-7
  • Kintex-7
  • Artix-7
  • MIG 7 Series