AR# 53925: v14.4 - How can designers set default PLB IP parameters in the MHS file for BSB generated projects?
v14.4 - How can designers set default PLB IP parameters in the MHS file for BSB generated projects?
The BSB (Base System Builder) tool in the EDK uses XBD (Xilinx Board Definition) files for PLB based designs.
Each development board has its own XBD file. The XBD (see chapter 10 of UG642)file will pull in all the available IP and set the default parameters for each IP for the particular FPGA. This XBD file is used for BSB to create a base project for the designer to evaluate a FPGA. This XBD file can be modified to pass design specific parameters to the BSB generated MHS file.
This can be achieved by using the IO_IS subproperty that is described on Page 123 of UG642, Platform Specification Format Reference Manual(EDK). This IO_IS subproperty needs to be added to the XBD file and the MPD file of the interface.
The following example is done by changing the UART MPD file and the ML507 XBD file.
For this example, the Baudrate of the UART is being set in the XBD file.
1) Add the PARAMETER C_BAUDRATE to the XBD file with IO_IS subproperty as below.
# 1st RS232 BEGIN IO_INTERFACE ATTRIBUTE INSTANCE = RS232_Uart_1 ATTRIBUTE IOTYPE = XIL_UART_V1 PARAMETER C_BAUDRATE = 115200, IO_IS = c_baudrate PORT RX = uart1_sin, IO_IS = serial_in PORT TX = uart1_sout, IO_IS = serial_out END
2) Then, in the UART Lite MPD, add the IO_IS subproperty as below: