UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53937

LogiCORE IP Serial RapidIO Gen2 v1.6 (ISE 14.4 / Vivado 2012.4) - phy_link_reset does not work

描述


Version Found: v1.6
Version Resolved and other Known Issues for v1.6 core: See (Xilinx Answer 52797)

In LogiCORE IP Serial RapidIO Gen2 v1.6 core, when asserting phy_link_reset, port_initialized signal does not deassert. In a previous core version, v1.5, it works without any issue.

解决方案

This is a known issue and will be fixed in the next release of the core.

If the design requires the use of phy_link_reset, please use v1.5 of the core.

Revision History
01/23/2013 - Initial release
AR# 53937
日期 01/23/2013
状态 Active
Type ??????
IP
  • Serial RapidIO
  • ??????
的页面