UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54004

Zynq-7000 AP SoC ZC702 Evaluation Kit - PMOD Header rise / fall time

描述

When using the PMOD headers on the Zynq-7000 AP SoC ZC702 Evaluation kit, while the voltage level output might appear normal at steady state, the rise / fall times on the other side of the level shifter might not be as expected.

解决方案

The maximum voltage output of the level shifter is 1.5V and the rise time can be several microseconds. The NDS331N FET used has a gate capacitance ~200 pF in this application.

The 200 pF load will affect maximum toggle rate, which would be ~100 kHz.

There are no speed requirements for PMOD or GPIOs. The recommendation for users looking for a specific high speed access with GPIO is to use the FMC interface instead.

AR# 54004
日期 11/08/2017
状态 Active
Type 综合文章
器件
  • Zynq-7000
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
的页面