AR# 5403

Constraints - Is there a way to add internal pull-ups/pull-downs in a device using the UCF (User Constraints File) or Constraints Editor?

描述

Keywords: pull-up, pullup, pull-down, pulldown, UCF, component, resistor, constraints, editor, add

Urgency: Standard

General Description:
Can I use a Constraints Editor or UCF file to add pull-ups or pull-downs to a pad?

The option to add a pull-up/pull-down in the Constraints Editor is not apparent.

(Furthermore, I occasionally encounter an error in NGDBuild stating that the UCF has invalid syntax at line ##, which is the "PULLUP" and "PULLDOWN" constraint.)

解决方案

1

(NOTE: User-configurable "PULLUPS" and "PULLDOWNS" are allowed for FPGA devices and CoolRunner CPLDs only. Please see (Xilinx Answer 7641) for information on CoolRunner CPLDs.)

The enabling of pull-up or pull-down resistors via the UCF file is supported ONLY in Xilinx software versions 2.1i and greater. The UCF syntax is as follows:

NET "pad_net_name" PULLDOWN;
or
INST "pad_instance_name" PULLDOWN;

NET "pad_net_name" PULLUP;
or
INST "pad_instance_name" PULLUP;

For more information, please refer to the Libraries Guide, Chapter 12 - "Attributes, Constraints, and Carry Logic" at:

"PULLDOWN" -
http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap12/lib12006.htm#BAJJEJEA

"PULLUP" -
http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap12/lib12006.htm#BAJCIJCA

In Xilinx software versions 1.5i and earlier, the only way to access the pull-ups or pull-downs is by instantiating the component. (There is no UCF support for these components.)

If you are using a schematic, select the pull-up/pull-down symbol and attach it to the pad net on which you wish to enable the resistors.

The following resolutions contain examples of VHDL and Verilog instantiations:

2

If using Verilog for your FPGA design, use the following:

// Instantiating PULLDOWN resistor
// Pulldowns can only be used in IOBs
// output TRI_SIG;

PULLDOWN U1 (.O(TRI_SIG));

// Instantiating PULLUP resistor
// Pullups can be used in IOBs or with
// Tri-state components (BUFT or BUFE) or
// Open-Drain components (DECODE, WAND, WORAND)
// wire TRI_SIG;

PULLUP U1 (.O(TRI_SIG));

3

If using VHDL for your FPGA design, use the following component instantiation:

-- Instantiating PULLDOWN resistor
-- Pulldowns can only be used in IOBs
-- TRI_SIG: std_logic;

component PULLDOWN
port (O: out std_logic);
end component;

-- Instantiating PULLUP resistor
-- Pullups can be used in IOBs or with
-- Tri-state components (BUFT or BUFE) or
-- Open-Drain components (DECODE, WAND, WORAND)
-- TRI_SIG: std_logic;

component PULLUP
port (O: out std_logic);
end component;

4

You may also add pull-ups/pull-downs in the Constraints Editor in 4.1 ISE/Foundation.

4.1i ISE: In Project Navigator, go to the "Processes for Current Source" window --> User Constraints --> Constraints Editor. In the Constraints Editor, go to the "Ports" tab and check the box next to "I/O Configuration Options". The pull-up/pull-down option will now be available in the "Port Name" rows.

4.1i Foundation: In Project Manager, at the top of the window, select Tools --> Implementation --> Constraints Editor. In the Constraints Editor, go to the "Ports" tab and check the box next to "I/O Configuration Options". The pull-up/pull-down option will now be available in the "Port Name" rows.
AR# 5403
日期 10/22/2008
状态 Archive
Type 综合文章