We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54108

14.4 EDK - AXI Quad SPI 1.00a has glitch between words


Between word transactions, there is a glitch on the MOSI line in the 1.00a version of the core, (See picture attached: 1.0_glitch). This may cause issues with on-board level shifters that have a minimum pulse-width of greater than the glitch, generally one reference clock.


This issue is rectified in the 2.00a version of the core. In the attached image (2.0_glitch), you will see the same transaction (0x55 followed by 0xAA), with no glitch on the MOSI line between words
AR# 54108
日期 02/04/2013
状态 Active
Type 综合文章
  • EDK - 14
  • AXI Quad SPI