The Parallel Cable IV is not supported in the Vivado tools. If I do not have an alternative cable to use, this means that I cannot access and use any debug cores that I add to my design in Vivado logic analyzer or Vivado serial I/O analyzer.
If designing in the Vivado tools, is there any way that I can add debug cores and use the Parallel Cable IV?
The Parallel Cable IV will not be supported in the Vivado tools. However, ChipScope analyzer supports this cable.
To work around this issue, you must ensure that you have the correct core versions as the Vivado debug cores.
You can match the core version to run time tools by using the following:
Debug IP Core and Version | Run-time Tool Requirement |
---|---|
AXI ChipScope Monitor, v3.05a (or earlier) | ChipScope Pro analyzer |
Integrated Controller (ICON), v1.06a (or earlier) | ChipScope Pro analyzer |
Integrated Logic Analyzer (ILA), v1.05a (or earlier) | ChipScope Pro analyzer |
Integrated Logic Analyzer (ILA), v2.0 (or later) | Vivado logic analyzer |
Virtual Input/Output (VIO), v1.05a (or earlier) | ChipScope Pro analyzer |
Virtual Input/Output (VIO), v2.0 (or later) | Vivado logic analyzer |
The same principle applies to IBERT cores:
Debug IP Core and Version | Run-time Tool Requirement |
---|---|
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTZ, v2.0 | ChipScope Pro analyzer or Vivado serial I/O analyzer |
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v3.0 (or later) | Vivado serial I/O analyzer |
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v2.02a | ChipScope Pro analyzer |
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v3.0 (or later) | Vivado serial I/O analyzer |
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v2.00a (or earlier) | ChipScope Pro analyzer |
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v3.0 (or later) | Vivado serial I/O analyzer |
Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v2.01a (or earlier) | ChipScope Pro analyzer |
To work around this issue, you need to include legacy debug cores in your Vivado design by following this procedure:
If you have some Vivado debug cores included in the design alongside your legacy debug cores added using the process above, there are some additional considerations.
AR# 54136 | |
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日期 | 01/30/2018 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools | |
IP | |
Boards & Kits |