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AR# 54161

Virtex-7 FPGA VC707 Evaluation Kit - Interface Test Designs

Description

I am attempting to exercise the interfaces on the Virtex-7 FPGA VC707 Evaluation Kit.

What tests can be run to ensure that the interfaces are working correctly?

解决方案

Virtex-7 FPGA VC707 Evaluation Kit Documentation and Example Designs referenced below can be found on the VC707 Support page.

Feature Test Design Notes
-- Configuration Interfaces --
Configuration Mode Switches VC707 User Guide (UG885) Table 1-2 has the valid settings.  Assuming configuration source is correctly programmed, this can test the mode pins
Configuration USB JTAG port VC707 BIST (XTP140 - ISE) (XTP205 - Vivado) See "Program VC707 with BIST Design" section
Configuration BPI Flash
VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
-- Board Feature Interfaces --
Board DDR3 SODIMM VC707 BIST (XTP140 - ISE) (XTP205 - Vivado) Also tested with the VC707 MIG Example Design
Board PCIe Edge Connector
VC707 PCIe Example Design (XTP144 - ISE) (XTP207 - Vivado)
Board SFP Connector VC707 GTX IBERT Example Design (XTP141 - ISE) (XTP210 - Vivado) Requires Molex 74765-0904
Board Oscillator (200 MHz, Differential) VC707 BIST (XTP140 - ISE) (XTP205 - Vivado) The default BIST examples use the socket clock
Board RJ45 - Ethernet VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
Board USB Serial UART VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
Board Power Monitoring Interface (TI PMBus) (Xilinx Answer 37561) Requires TI USB EVM Adapter; see (Xilinx Answer 54022)
Board I2C Interface VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
Board FMC-HPC Connector XM105 User Guide (UG537) Page 29. This is the User Guide for the XM105 Mezzanine Debug Card.  This card has DS5, DS6, and DS7, which indicate good power to the board. Debug strategies will vary depending on the specific mezzanine card being used.
Board XADC Interface Virtex-7 FPGA VC707 Evaluation Kit AMS Targeted Reference Design and 7-Series AMS TRD User Guide (UG960) Requires AMS101 card
-- Transceiver Interfaces --
Transceiver RefCLK (differential)
VC707 GTX IBERT (XTP141 - ISE) (XTP210 - Vivado) This is the IBERT Example Design and could be modified to use SMA RefCLK
Transceiver SMA Connectors (Differential) VC707 GTX IBERT (XTP141 - ISE) (XTP210 - Vivado)
-- User Specified Interfaces --
User CLK Socket Connector (Single-Ended) VC707 BIST (XTP140 - ISE) ( XTP205 - Vivado) All designs in the BIST use the socket clock source
User SMA CLK Connectors (Differential) none available These are completely user-driven I/O.  A good test would be loop back or monitoring differential I/O on a scope
User SMA Connectors (Differential) none available These are completely user-driven I/O
User LEDs
VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
User DIP Switches
VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
User Pushbuttons
VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)
User LCD Display VC707 BIST (XTP140 - ISE) (XTP205 - Vivado)

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Answer Number 问答标题 问题版本 已解决问题的版本
43748 Xilinx Boards and Kits - Debug Assistant N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
51233 Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist N/A N/A
AR# 54161
创建日期 02/06/2013
Last Updated 01/20/2014
状态 Active
Type 综合文章
Boards & Kits
  • Virtex-7 FPGA VC707 Evaluation Kit