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AR# 54174

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (ISE 14.4/Vivado 2012.4) - GTX transceiver CPLL can become inoperative on certain conditions


Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When using 7 Series (Virtex-7 and Kintex-7) GTX in GES or earlier silicon revision, the CPLL should never be powered down. This issue affects the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core and also third party cores that do powerdown of the GTs in the wrapper. The workaround below also applies to the third party cores. For more information, please contact the corresponding vendor of the core.

The current Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 core PIPE Wrapper powers down the CPLL when entering Gen3 for power savings.


1. The CPLL power-down issue in the PIPE Wrapper is limited to the following condition only:
PCIE_LINK_SPEED = 3 AND Gen3 rate change.

If user sets PCIE_LINK_SPEED = 3, but never enters Gen3, then this issue can be ignored.

2. Please refer to the following link for 7 series FPGAs Errata:


To work around this issue, set the CPLL powerdown port CPLLPD to 1'b0 on all lanes. Make the following modification in <core_name>_pipe_wrapper.v file in the 'source' directory.


.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),


.GT_CPLLPD (1'd0),

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
02/15/2013 - Initial Release
AR# 54174
日期 03/05/2013
状态 Active
Type 已知问题
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)