Alwaysrefer tothe trce timing results for timing analysis completion.
The followingapplies to ISE14.x Speedprint, whichincludes Multi-CornerTimingAnalysis.
For each timing delay name, Speedprint will report minimum and maximum values for both fast silicon and slow silicon.If all paths for a given delay name have the same value, then the output will look like:
Timing Delay Name (fmin/fmax) (smin/smax)
A single timing delay name may be used for different paths, and can have different values. In the case where a timing delay name has more than one set of values, speedprint will report two sets of max and min values representing the slowest path information and the fastest path information, as such:
Timing Delay Name (fmin/fmax, fmin/fmax) (smin/smax, smin/smax)
fmin: minimum delay for fast silicon
fmax: maximum delay for fast silicon
smin: minimum delay for slow silicon
smax: maximum delay for slow silicon