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AR# 54209

Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.2) - EMCCLK settings for Linear BPI Flash Memory configuration incorrect

Description

The VC707 Evaluation Board User Guide v1.2 (UG885), page 15 and 16 discusses the Linear BPI Flash Memory on the Virtex-7 FPGA VC707 Evaluation Kit.

This section describes the data rate as up to 40 MHz, and outlines that the fastest configuration method uses the external 80 MHz oscillator connected to the FPGA's EMCCLK pin with a bitstream that has been built to divide the configuration clock by two.

Page 72 also describes the fastest configuration speed as 40 MHz, with the bitgen option to divide the EMCCLK by two.

Is this information accurate?

解决方案

The VC707 Evaluation Board User Guide v1.2 (UG885) lists the data rate for the Linear BPI Flash Memory as 40 MHz; this should read 80 MHz.

As the 80 MHz data rate is supported, the fastest configuration method then uses the external 80 MHz oscillator connected to the FPGA's EMCCLK pin with a bitstream that has been built to divide the configuration clock by one.

The VC707 Evaluation Board User Guide (UG885) v1.3 has been updated to reflect this information.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45382 Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 54209
创建日期 02/11/2013
Last Updated 01/10/2014
状态 Active
Type 综合文章
Boards & Kits
  • Virtex-7 FPGA VC707 Evaluation Kit