This answer record contains the Release Notes and Known Issues for the 10-Gigabit Ethernet MAC Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE 10-Gigabit Ethernet MAC Core IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v15.0 (Rev. 3)||2015.4|
|v15.0 (Rev. 2)||2015.3|
|v15.0 (Rev. 1)||2015.2|
|v14.0 (Rev. 1)||2014.4|
|v13.1 (Rev. 1)||2014.2|
|v13.0 (Rev. 1)||2013.4|
|v12.0 (Rev. 1)||2013.2|
The following table provides answer records for general guidance when using the LogiCORE 10-Gigabit Ethernet MAC core.
|(Xilinx Answer 38279)||Ethernet IP Solution Center|
|(Xilinx Answer 55077)||Ethernet IP Cores - Design Hierarchy in Vivado|
Known and Resolved Issues
The following table provides known and resolved issues for the 10-Gigabit Ethernet MAC core, starting with v12.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|NA||Fixed corner case RX issue - If there is a cable pull event as soon as the frame starts then AXI-S tvalid may not be de-asserted||v15.1(rev.1)||v15.1(rev.2)|
|NA||Fixed Example Design RX FIFO 64-bit - Read does not stop immediately when fifo_tready is deasserted soon after the last word has been read-out from FIFO||v15.1(rev.1)||v15.1(rev.2)|
|NA||Fixed RX statistics issue - Statistics vector bit 29 is wrongly asserted for padded VLAN and normal frames||v15.1(rev.1)||v15.1(rev.2)|
|(Xilinx Answer 66822)||AXI 10G Ethernet Subsystem - Frame Errors seen in Example design Simulation and Hardware.||v15.0 (Rev. 3)||v15.1|
|NA||Corner case RX issue - Frames with bad CRC were not dropped when the frame's composition matched a certain pattern||v15.0 (Rev. 2)||v15.1|
|NA||Corner case TX issue - Error codes were not transmitted when implicit error and frame oversize error events occur at the same time||v15.0 (Rev. 2)||v15.1|
|NA||Fixed bugs in 64-bit Example design FIFO which caused frames to be dropped||v15.0 (Rev. 1)||v15.1|
|NA||Fixed RX Issue - Frames, which had L/T field indicating length, were not dropped if the L/T field did not match the actual packet length||v15.0 (Rev. 1)||15.1|
|NA||Fixed RX Stats Issue - RX Statistics bit 29 is not asserted for frames which had L/T field indicating length when the L/T field was incorrect||V15.0||v15.1|
|NA||Explicit Underrun when using DIC could result in following frame being corrupted||v14.0||v15.0|
|(Xilinx Answer 63106)||AXI lite interface failures seen when using 64-bit master||v14.0||v15.0|
|(Xilinx Answer 63212)||Potential lock up issue with Example Design receive AXI-stream FIFO||v14.0||v15.0|
|(Xilinx Answer 63439)||Example Design TX FIFO only operates at full throughput if In-band FCS and custom preamble are disabled||v14.0||v15.0|
|NA||Corner case - Oversized VLAN frame of size 1524 bytes can be incorrectly transmitted without XGMII error codes when the TX configuration is as follows: Jumbo frames and MTU disabled; VLAN enabled; In-band FCS enabled.||v13.0||v14.0|
|NA||Example design Transmit FIFO could hang if frame sizes larger than the FIFO memory size are sent for transmission||v13.0||v14.0|
|(Xilinx Answer 59891)||Additional XDC constraints for the MDIO signal inputs to ease timing closure||v13.0||v13.1|
|(Xilinx Answer 59308)||Fragmented frame counted as undersized frame instead of a fragment in the RX statistics counters||v13.0||v13.1|
|(Xilinx Answer 60197)||TX Statistics - Correction to oversized frame count||v13.0||v13.1|
|N/A||Corner case - RX Statistics - sometimes RX statistics vector bit 29 not asserted when runt frame received||v13.0||v13.1|
|N/A||Corner case - Transmitting Frame - TX Frame following runt frame could have illegal Start code and IFG||v13.0||v13.1|
|N/A||Corner case - Custom Preamble - Out of reset, first frame transmitted could contain previous custom preamble (if custom preamble was enabled prior to reset, but disabled after reset)||v13.0||v13.1|
|(Xilinx Answer 55131)||Artix-7 Devices - WAN mode - Marginal timing seen||v12.0||See work-around in answer record|
|(Xilinx Answer 55038)||VHDL Example Design - Internal XGMII interface; tx_dcm_locked port not driven||v12.0||v12.0 (Rev. 1)|
|N/A||Receive Out Of bounds frames were not being counted in statistics if followed immediately by another frame.||v11.5||v12.0|
|N/A||Received 12 byte undersized frame marked good||v11.5||v12.0|
|N/A||Transmitter hangs when sending 63 byte frame with inband FCS passing||v11.5||v12.0|
|N/A||Occasionally first frame transmitted after power up seen to have incorrect FCS||v11.5||v12.0|
|N/A||10GEMAC does not enforce minimum IFG on TX after erroring frame||v11.5||v12.0|