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AR# 54274

Zynq-7000 Example Design - IP Integrator AXI3 Master

Description

This design connects a custom AXI3 master to each of the Zynq AXI slaves: AXI_HP0-3, AXI_GP0-1, and AXI_ACP.

The custom core performs a simple incrementing value memory test to DDR. The error bits are routed to the GPIO; failures occur if any bit is set to '1'.

Note: AXI4 masters are recommended for new designs instead of AXI3. The AXI3 master in this design is used to demonstrate the highest frequencies to the Zynq-7000 AXI interfaces.

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. 

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. 

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.

解决方案

Implementation Details
Design TypePS & PL
SW TypeNone
CPUsN/A
PS FeaturesDDRC, ACP, AXI_GP, AXI_HP
PL CoresAXI Register Slice
Boards/Toolszc702
Xilinx Tools VersionVivado 2017.1
Other detailsDesign closes timing at 250 MHz.
Address Map
Base Address
axi3_master_hp00x10000000
axi3_master_hp10x11000000
axi3_master_hp20x12000000
axi3_master_hp30x13000000
axi3_master_gp00x14000000
axi3_master_gp10x15000000
axi3_master_acp0x16000000
PS GPIO Error bits
0xE000A068
Files Provided
xilinx.com_user_axi3_master_1.0.zipCustom AXI3 master.
ar54274_bd.tclBlock Diagram
xmd.ini
commands to load design via XMD.
Block Diagram


 

Directions:

  1. Extract the zip to a directory, create a zc702 project, and then add the directory as a repository preference.
  2. Type the following in the Tcl Console, 'source ar54274_bd.tcl'.
  3. Generate Bitstream.
  4. Select File -> Export to SDK.
  5. Place xmd.ini into the exported SDK directory, change to that directory, and run xmd. This will load and start the design.
  6. In XMD, use 'mrd 0xE000A068' to check the status of the Error bits.

Attachments

文件名 文件大小 File Type
xmd.ini 423 Bytes INI
axi3_master.zip 12 KB ZIP
ar54274_bd.tcl 22 KB TCL
AR# 54274
日期 05/22/2017
状态 Active
Type 综合文章
器件
  • Zynq-7000
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit