This design connects a custom AXI3 master to each of the Zynq AXI slaves: AXI_HP0-3, AXI_GP0-1, and AXI_ACP.
The custom core performs a simple incrementing value memory test to DDR. The error bits are routed to the GPIO; failures occur if any bit is set to '1'.
Note: AXI4 masters are recommended for new designs instead of AXI3. The AXI3 master in this design is used to demonstrate the highest frequencies to the Zynq-7000 AXI interfaces.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.
|Design Type||PS & PL|
|PS Features||DDRC, ACP, AXI_GP, AXI_HP|
|PL Cores||AXI Register Slice|
|Xilinx Tools Version||Vivado 2017.1|
|Other details||Design closes timing at 250 MHz.|
|PS GPIO Error bits||0xE000A068|
|xilinx.com_user_axi3_master_1.0.zip||Custom AXI3 master. |
|xmd.ini||commands to load design via XMD. |
|Boards & Kits||