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AR# 54276

CONSTRAINTS : How can I constrain asynchronous paths from the clock resources?


I have a design where Clear (CLR), Chip Enable (CE) and other signals from the Clocking resources structure are not reported in my Timing Report.

How can I constrain those asynchronous paths to these particular signals?


It is possible to constrain those particular paths by doing the following:

  1. Using "Timing Point Synchronization" (TPSYNC):
    This is a grouping constraint which flags a particular point or set of points for Timing analysis.
    It can be used directly in a NET/INSTANCE or PIN, and when applied to the output of the primitive, it automatically selects all of the inputs.
    Syntax UCF:
    NET/INSTANCE/PIN  "net/instance/pin name" TPSYNC = identifier
        TIMESPEC TS01 = TO tpsync_identifer value units;
    If the identifier is used with other elements, then the constraint groups all of them for Timing analysis.

  2. For cases where TPSYNC does not work well, it is also possible to use "Maximum Delay" (MAXDELAY).
    This constraint defines the maximum allowable delay on a net.
    This is the case for some clocking resources such as BUFR.
    In those particular cases, due to the lack of technology characterization, the Timing report does not recognize the path connected to CLR and CE pins and MAXDELAY must be used. 
    Syntax UCF: NET "net name" MAXDELAY = value units; 

For more information about these constraints, refer to (UG625)

AR# 54276
日期 01/07/2015
状态 Active
Type 设计咨询
  • FPGA Device Families
  • ISE Design Suite