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AR# 54279

Kintex-7 FPGA KC705 Evaluation Kit - Interface Test Designs

Description

I am attempting to exercise the interfaces on the Kintex-7 FPGA KC705 Evaluation Kit.

What tests can be run to ensure that the interfaces are working correctly?

解决方案

Kintex-7 FPGA KC705 Evaluation Kit Documentation and Example Designs referenced below can be found on the KC705 Support page.

Feature Test Design Notes
-- Configuration Interfaces --
Configuration Mode Switches KC705 User Guide (UG810) Table 1-2 has the valid settings.  Assuming configuration source is correctly programmed, this can test the mode pins
Configuration USB JTAG port KC705 BIST (XTP102 - ISE) (XTP195 - Vivado) See "Program KC705 with BIST Design" section
Configuration BPI Flash
KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
-- Board Feature Interfaces --
Board DDR3 SODIMM KC705 BIST (XTP102 - ISE) (XTP195 - Vivado) Also tested with the KC705 MIG Example Design
Board PCIe Edge Connector
KC705 PCIe Example Design (XTP106 - ISE) (XTP197 - Vivado)
Board SFP Connector KC705 GTX IBERT Example Design
(XTP103 - ISE)  (XTP200 - Vivado)
Requires Molex 74765-0904
Board Oscillator (200 MHz, Differential) KC705 BIST (XTP102 - ISE) (XTP195 - Vivado) The default BIST examples use the socket clock
Board RJ45 - Ethernet KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
Board USB Serial UART KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
Board Power Monitoring Interface (TI PMBus) (Xilinx Answer 37561) Requires the TI USB Interface Adapter EVM; See (Xilinx Answer 54022)
Board I2C Interface KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
Board FMC-HPC Connector XM105 User Guide (UG537) Page 29.  This is the User Guide for the XM105 Mezzanine Debug Card.  This card has DS5, DS6, and DS7, which indicate good power to the board.  Debug strategies will vary depending on the specific mezzanine card being used.
Board XADC Interface Kintex-7 FPGA KC705 Evaluation Kit AMS Targeted Reference Design and 7-Series AMS TRD User Guide (UG960) Requires AMS101 card
-- Transceiver Interfaces --
Transceiver RefCLK (differential)
KC705 GTX IBERT Example Design (XTP103 - ISE) (XTP200 - Vivado) This is the IBERT Example Design and could be modified to use SMA RefCLK
Transceiver SMA Connectors (Differential) KC705 GTX IBERT Example Design
(XTP103 - ISE) (XTP200 - Vivado)
-- User Specified Interfaces --
User CLK Socket Connector (Single-Ended) KC705 BIST (XTP102 - ISE) ( XTP195 - Vivado) All designs in the BIST use the socket clock source
User SMA CLK Connectors (Differential) none available These are completely user-driven I/O.  A good test would be loop back or monitoring differential I/O on a scope
User SMA Connectors (Differential) none available These are completely user-driven I/O
User LEDs
KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
User DIP Switches
KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
User Pushbuttons
KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)
User LCD Display KC705 BIST (XTP102 - ISE) (XTP195 - Vivado)

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Answer Number 问答标题 问题版本 已解决问题的版本
43748 Xilinx Boards and Kits - Debug Assistant N/A N/A
AR# 54279
创建日期 02/19/2013
Last Updated 01/22/2014
状态 Active
Type 综合文章
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit