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Virtex-7, Vivado SIOD - GTH 2.01 fails timing using the example design
If using a Vivado Serial I/O Debug (SIOD) 2.01 core for a GTH on a Virtex 7 X980T 1926-2L, timing errors are seen in the example design when the following settings are selected:
- 1 quad (quad 217), running at 11.2 Gb/s, 32-bit data, using the quad PLL
- QUAD 217 REFCLK1 at 175 MHz
- Channel 0 TXUSRCLK source
- No external system clock
This is a known issue and will be fixed in a future revision of the tools.
- ChipScope Pro IBERT for 7 Series GTH