If the DDR device mentions it is back compatible with the slower speed grade, the specifications of both speed grades are available to be used.
To achieve maximum bandwidth, EDK XPS selects the better setting to generate ps7_init for inclusion into the FSBL.
For more information on proper settings, contact the device vendor, and override with a custom setting in the Xilinx tools.
| AR# 54398 | |
|---|---|
| 日期 | 05/28/2018 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 |
|