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AR# 54448

LogiCORE IP AXI Video Direct Memory Access - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

描述

This answer record contains the Release Notes and Known Issues for the AXI Video Direct Memory Access Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

AXI Video Direct Memory Access LogiCORE IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi_video_dma.html

解决方案

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Linux Drivers - Xilinx Wiki

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core
Version
Vivado Tools
Version
IP ChangelogIP PatchesStandalone Software Driver Patches
v6.3 (Rev. 7)2019.1(Xilinx Answer 72242)
v6.3 (Rev. 6)2018.3(Xilinx Answer 71806)
v6.3 (Rev. 5)2018.2(Xilinx Answer 71212)
v6.3 (Rev. 4)2018.1(Xilinx Answer 70699)
v6.3 (Rev. 3)2017.4(Xilinx Answer 70386)
v6.3 (Rev. 2)2017.3(Xilinx Answer 69903)
v6.3 (Rev. 1)2017.2(Xilinx Answer 69326)
v6.32017.1(Xilinx Answer 69055)
v6.2 (Rev. 10)2016.4(Xilinx Answer 68369)
v6.2 (Rev. 9)
2016.3(Xilinx Answer 68021)
v6.2 (Rev. 8)
2016.2(Xilinx Answer 67345)
v6.2 (Rev. 7)
2016.1(Xilinx Answer 66930)
v6.2 (Rev. 6)2015.4(Xilinx Answer 66930)
v6.2 (Rev. 5)2015.3
v6.2 (Rev. 4)2015.2
v6.2 (Rev. 3)2015.1
v6.2 (Rev. 2)2014.3
v6.2 (Rev. 1)2014.2
v6.22014.1
v6.1 (Rev. 1)2013.4
v6.12013.3
v6.0 (Rev 1)2013.2
v6.02013.1


General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE AXI Video Direct Memory Access core.

Answer RecordTitle
(Xilinx Answer 72543)When should I use the VDMA and when should I use the Video Frame Buffer?
(Xilinx Answer 70221)What are the throughput limitations of the VDMA?
(Xilinx Answer 66493)How to get an interrupt at the end of a frame?
(Xilinx Answer 60895)How does the VDMA pack and unpack data if the AXI4-Stream write (S2MM) and read (MM2S) are different widths?
(Xilinx Answer 59413)Occasional AXI Lite Failures
(Xilinx Answer 58158)Core not transferring data when used in a processor-less IPI system
(Xilinx Answer 54878)Throughput/Bandwidth limitations
(Xilinx Answer 55218)Horizontal shear/shift in output video
(Xilinx Answer 55221)Low frame rate/choppy video
(Xilinx Answer 54934)Throttling, frame size errors (SOF), and/or unexpected TKEEP behavior
(Xilinx Answer 53281)Recommendations for handling FSYNC


Known and Resolved Issues

The following table provides known issues for the AXI Video Direct Memory Access core, starting with v6.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion
Found
Version
Resolved
(Xilinx Answer 71984)Design on a 7 Series device fails to meet timing with a VDMA in asynchronous modev6.3 (Rev. 2)N/A
(Xilinx Answer 56989)FAILURE : Behavioral models do not support built-in FIFO configurationsv6.0N/A
(Xilinx Answer 56623)S2MM_TREADY stays deasserted in my IP Integrator designv6.0 (Rev. 1)v6.1
(Xilinx Answer 55183)Post-synthesis netlist simulation errors targeting defense grade and/or low power devicesv6.0v6.0 (Rev. 1)

 

Please seek technical support via the Video Board. The Xilinx Forums are a great resource for technical support.

The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Revision History
07/16/2016Added (Xilinx Answer 72543)
05/20/2016Added v6.3 (Rev. 7) to version table
02/01/2019Added (Xilinx Answer 71984) to the Known and Resolved issues table
01/4/2019Added  v6.3 (Rev. 4), v6.3 (Rev. 5), v6.3 (Rev. 6) to the version table.
01/12/2018Added v6.2 (Rev. 3), v6.2 (Rev. 4), v6.2 (Rev. 5), v6.2 (Rev. 6), v6.2 (Rev. 7), v6.2 (Rev. 8), v6.3, v6.3 (Rev. 1), v6.3 (Rev. 2), v6.3 (Rev. 3) to the version table.
Added (Xilinx Answer 70221).
01/29/2016Added (Xilinx Answer 66493).
09/09/2014Added v6.2 (Rev. 2) to the version table. Added (Xilinx Answer 59413).
08/18/2014Added v6.1 (Rev. 1), v6.2, and v6.2 (Rev. 1) to the version table. Added (Xilinx Answer 60895).
10/28/2013Added (Xilinx Answer 58158).
10/23/2013Added v6.1 to the version table.
04/03/2013Initial release.

 

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
55183 LogiCORE IP AXI Video Direct Memory Access v6.0 - Post-synthesis netlist simulation errors targeting defense grade or low power devices N/A N/A
54878 LogiCORE IP AXI Video Direct Memory Access - Throughput/Bandwidth Limitations N/A N/A
55218 LogiCORE IP AXI Video Direct Memory Access - Horizontal shear/shift in output video N/A N/A
55221 LogiCORE IP AXI Video Direct Memory Access - Low frame rate/choppy video N/A N/A
53281 LogiCORE IP AXI Video Direct Memory Access - Recommendations for handling FSYNC N/A N/A
56623 LogiCORE IP AXI Video Direct Memory Access v6.0 - S2MM_TREADY stays deasserted in my IPI design N/A N/A
56989 LogiCORE IP AXI Video Direct Memory Access v6.0 - "FAILURE : Behavioral models do not support built-in FIFO configurations" N/A N/A
58158 LogiCORE IP AXI Video Direct Memory Access - Core not transferring data when used in a processor-less IPI system N/A N/A
60895 LogiCORE IP AXI Video Direct Memory Access - How does the VDMA pack and unpack data if the AXI4-Stream write (S2MM) and read (MM2S) are different widths? N/A N/A
59413 LogiCORE IP AXI Video Direct Memory Access - Occasional AXI Lite failures N/A N/A
66493 LogiCORE IP AXI Video Direct Memory Access v6.2 - How to get an interrupt at the end of the frame? N/A N/A
70221 LogiCORE IP AXI Video Direct Memory Access v6.3 - What are the throughput limitations of the VDMA? N/A N/A
71984 AXI VDMA v6.3 - Design on a 7 Series device fails to meet timing with a VDMA in asynchronous mode N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
47654 AXI Video Direct Memory Access (VDMA) - Release Notes and Known Issues N/A N/A
61625 Video IP Example Design Landing Page N/A N/A
AR# 54448
日期 07/22/2019
状态 Active
Type 版本说明
Tools
IP
的页面