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AR# 54448

LogiCORE IP AXI Video Direct Memory Access - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the AXI Video Direct Memory Access Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

AXI Video Direct Memory Access LogiCORE IP Page:



General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Vivado Tools
v6.3 (Rev. 3)2017.4
v6.3 (Rev. 2)2017.3
v6.3 (Rev. 1)2017.2
v6.2 (Rev. 8)2016.3
v6.2 (Rev. 7)2016.2
v6.2 (Rev. 6)2016.1
v6.2 (Rev. 5)2015.3
v6.2 (Rev. 4)2015.2
v6.2 (Rev. 3)2015.1
v6.2 (Rev. 2)2014.3
v6.2 (Rev. 1)2014.2
v6.1 (Rev. 1)2013.4
v6.0 (Rev 1)2013.2

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE AXI Video Direct Memory Access core.

Answer RecordTitle
(Xilinx Answer 70221)What are the throughput limitations of the VDMA?
(Xilinx Answer 66493)How to get an interrupt at the end of a frame?
(Xilinx Answer 60895)How does the VDMA pack and unpack data if the AXI4-Stream write (S2MM) and read (MM2S) are different widths?
(Xilinx Answer 59413)Occasional AXI Lite Failures
(Xilinx Answer 58158)Core not transferring data when used in a processor-less IPI system
(Xilinx Answer 54878)Throughput/Bandwidth limitations
(Xilinx Answer 55218)Horizontal shear/shift in output video
(Xilinx Answer 55221)Low frame rate/choppy video
(Xilinx Answer 53281)Recommendations for handling FSYNC

Known and Resolved Issues

The following table provides known issues for the AXI Video Direct Memory Access core, starting with v6.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion
(Xilinx Answer 56989)FAILURE : Behavioral models do not support built-in FIFO configurations v6.0N/A
(Xilinx Answer 56623)S2MM_TREADY stays deasserted in my IP Integrator designv6.0 (Rev. 1)v6.1
(Xilinx Answer 55183)Post-synthesis netlist simulation errors targeting defense grade and/or low power devices v6.0v6.0 (Rev. 1)

Revision History

01/12/2018Added v6.2 (Rev. 3), v6.2 (Rev. 4), v6.2 (Rev. 5), v6.2 (Rev. 6), v6.2 (Rev. 7), v6.2 (Rev. 8), v6.3, v6.3 (Rev. 1), v6.3 (Rev. 2), v6.3 (Rev. 3) to the version table.
Added (Xilinx Answer 70221).
01/29/2016Added (Xilinx Answer 66493).
09/09/2014Added v6.2 (Rev. 2) to the version table. Added (Xilinx Answer 59413).
08/18/2014Added v6.1 (Rev. 1), v6.2, and v6.2 (Rev. 1) to the version table. Added (Xilinx Answer 60895).
10/28/2013Added (Xilinx Answer 58158).
10/23/2013Added v6.1 to the version table.
04/03/2013Initial release.





Answer Number 问答标题 问题版本 已解决问题的版本
47654 AXI Video Direct Memory Access (VDMA) - Release Notes and Known Issues N/A N/A
61625 Video IP Example Design Landing Page N/A N/A
AR# 54448
日期 01/22/2018
状态 Active
Type 版本说明
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
  • AXI Video Direct Memory Access