UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5445

V1.5 CORE Generator, Foundation - Bus Conflict errors during Foundation functional and timing simulation of NCO modules

Description

Keywords: functional, timing, simulation, NCO, conflict errors

Urgency: Standard

General Description:
Numerous bus conflict errors on signals internal to the NCO
may be seen in both functional and timing simulations in
Foundation for NCO's with amplitude and phase bit widths of 8
bits or higher.

No similar errors are observed in HDL simulation.

解决方案

The bus conflicts are associated with the use of TBUFs
for muxing in NCOs when phase and amplitude bit widths
are specified to be 8 bits or wider. There is a small possibility
of such bus conflicts occurring in the actual hardware, so the
modeling of this situation in the Foundation simulator is not invalid.

In both the HDL and Foundation gate-level simulation models,
there will be a momentary instant (while one TBUF is turning
on, and the other is switching OFF) during which both TBUFs
are driving the same line with different values. This
contention situation results in an "unknown-X" contention
state on the output node.

The difference between the Foundation gate-level simulator
and HDL simulators is that Foundation can differentiate
between a generic "unknown-X" state and a "conflict" unknown-X.
The latter is reported as a special class of error called
a "bus conflict".

In the Xilinx Verilog and VHDL UniSim models, the duration of the
conflict defaults to 100ps in functional simulation. On the other
hand, Foundation functional simulation uses a "delta cycle" concept
similar to that used in VHDL simulators. In this case, the duration of the
conflict in functional simulation is a single delta cycle of length 0 ns.
The simulator will only issue warnings about the bus conflicts for a
functional simulation, but will not actually display the errors in the
waveform. If you wish to actually visualize these errors, you must run
a Foundation UNIT delay simulation, as it will use the non-zero simulation
precision value as the time unit (also 100ps by default).

In the actual hardware:

1. The 3-state Longline drivers are designed such that they
turn off faster than they turn on, so the actual prospect
of bus contention is usually minimal.

2. Even if there is a short moment of internal contention, the
Icc current is less than 10 mA per line, so it is tolerable,
even for a 16-bit bus. Generous Vcc decoupling should be
exercised to minimize the possibility of such a spike.

If the bus conflict errors during Foundation simulation prove
to be too obtrusive, they can be disabled within the
simulator by deselecting the "bus conflict" option in the
Simulator Options menu:

From the Options menu, select "Preferences" and click on
the Reports tab. From here you may selectively disable
display, registering and/or reporting of Bus Conflicts.
AR# 5445
创建日期 08/31/2007
Last Updated 02/15/2001
状态 Archive
Type ??????