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AR# 54460

Soft Error Mitigation Controller - How to use SEM IP with Vivado Lab Tools

Description

The flow described in this answer record indicates how to modify the SEM example design and bring up the signals in Vivado Lab Tools (i.e., via open hardware session).

 

There are two separate sets of instructions,

  • For 2013.2 and earlier using SEM v4.0 rev1 and earlier.
     
  • For 2013.3 and using SEMv4.0 rev2 or later.

解决方案

2013.2 and earlier using SEM v4.0 rev1 and earlier

  1. Customize the Soft Error Mitigation IP, selecting the "chipscope" option for Error Injection Shim.
  2. Click OK.
  3. Right-click on the configured IP and select "Open IP Example Design."
  4. Within the IP Example Design, double-click to open the "example_hid" HDL source file, and comment out both the "chipscope_icon" and "chipscope_vio" instances.
    For VHDL configurations, also comment out the corresponding component declarations.
  5. In replacement of the commented "chipscope_vio" instance, manually instantiate a new vio instance as follows:

    Verilog:
      sem_vio example_chipscope_vio (
        .CLK(icap_clk),
        .PROBE_IN0(sync_in),
        .PROBE_OUT0(sync_out)
      );
    VHDL:
      example_chipscope_vio : sem_vio
      port map (
        CLK => icap_clk,
        PROBE_IN0 => sync_in,
        PROBE_OUT0 => sync_out
        );
  6. For VHDL configurations, also create a corresponding component declaration. Port widths are unchanged.
  7. Save the modified HDL file.
  8. Make note of the vector width of the "sync_in" signal, declared earlier in the file.
  9. Open the IP Catalog and double-click to customize the "VIO (Virtual Input/Output)" IP.
  10. In the Customize IP window, make the following changes to the default VIO IP options:
    1. Change the Component Name to "sem_vio"
    2. From the PROBE_IN Ports tab, change with Probe Width of PROBE_IN0 to the noted vector width of the sync_in signal.
    3. From the PROBE_OUT Ports tab, change with Probe Width of PROBE_OUT0 to 41.
    4. Click OK to complete customization of the VIO IP.
  11. Ensure that the newly-customized "sem_vio" instance is shown under the "example_hid" design source hierarchy.
  12. Complete design implementation as usual.
  13. Upon programming the FPGA, choose "Open Hardware Session," and note the presence of the VIO instance in the "Debug Probes" window. The VIO ports and their usage are described in the Soft Error Mitigation Controller Product Guide, PG036.

 

 

2013.3 and using SEMv4.0 rev2 or later

1.       Customize the Soft Error Mitigation IP, selecting the "ChipScope" option for Error Injection Shim.
 
2.       Click OK.
 
3.       Right-click on the configured IP and select "Open IP Example Design."
 
4.       Within the IP Example Design, replace the "example_hid" HDL source file with one of the HDL files in the zip attached to this Answer Record.

          Follow these steps:
 
  1. Select the example_hid file in the design source hierarchy, and note the path of the file.
     
  2. Download the zip file from this Answer Record.
     
  3. Unzip the file.
    There are 4 different example_hid files provided in this zip.
    Select the file appropriate to the target device and HDL language:
     
    •    ./monolithic_verilog/sem_0_sem_hid.v
    •    ./ssi_verilog/sem_0_sem_hid.v
    •    ./monolithic_vhdl/sem_0_sem_hid.vhd
    •    ./ssi_vhdl/sem_0_sem_hid.vhd

    (Note: Devices that contain 7vx1140t, 7vh580t, 7vh870t, or 7v2000t are considered Virtex-7 SSI devices. All other devices are considered Monolithic)

  4. Replace the IP Example Design example_hid file with the selected file.
    The sample HDL files provided with this Answer Record use the default component name sem_0. 
    Update the module or component declarations as needed to integrate this sample file into the project.
     
  5. In the Vivado design source hierarchy, ensure that the new file is correctly reflected in the hierarchy.
    This update should occur automatically. If not, update by right-clicking on the hierarchy pane and selecting refresh hierarchy.
     
5.       Open the IP Catalog, go to Debug & Verification -> Debug -> "VIO (Virtual Input/Output)", and double-click to customize.
 
6.       In the Customize IP window, make the following changes to the default VIO IP options:
 
  • Change the Component Name to "sem_vio"
  • If the target device is a Virtex-7 SSI device:
    From the PROBE_IN Ports tab, change the number of PROBE_IN ports to 4, and set all PORT_WIDTHS to 8. 
    From the PROBE_OUT ports Tab, change the number of PROBE_OUT ports to 2, and set the PROBE_OUT0_WIDTH to 1, and PROBE_OUT1_WIDTH to 40
  • For all other devices:
    From the PROBE_IN Ports tab, change the number of PROBE_IN ports to 8, and set all PORT_WIDTHS to 1
    From the PROBE_OUT ports Tab, change the number of PROBE_OUT ports to 2, and set the PROBE_OUT0_WIDTH to 1, and PROBE_OUT1_WIDTH to 40
  • Click OK to complete customization of the VIO IP.
  Ensure that the newly-customized "sem_vio" instance is shown under the "example_hid" design source hierarchy.

7.       Complete design implementation as usual.
 
8.       Upon programming the FPGA, choose "Open Hardware Session," and note the presence of the VIO instance in the "Debug Probes" window.
          The VIO ports and their usage are described in the Soft Error Mitigation Controller Product Guide, PG036.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54642 Soft Error Mitigation IP Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 54460
创建日期 02/22/2013
Last Updated 10/22/2014
状态 Active
Type 综合文章
Tools
  • Vivado Design Suite - 2013.1
IP
  • Soft Error Mitigation