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  3. AR# 54472: IP Release Notes and Known Issues for LogiCORE IP 3GPP Turbo Encoder (TCC) core for Vivado 2013.1 and newer tool versions

AR# 54472

IP Release Notes and Known Issues for LogiCORE IP 3GPP Turbo Encoder (TCC) core for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP 3GPP Turbo Encoder (TCC) core and includes the following:
 
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP 3GPP Turbo Encoder (TCC) core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/do-di-tccenc.html

解决方案

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
 
Core Version Vivado Tools Version
v5.0(Rev. 6) 2014.4
v5.0(Rev. 5) 2014.3
v5.0(Rev. 4) 2014.2
v5.0(Rev. 4) 2014.1
v5.0(Rev. 3) 2013.4
v5.0(Rev. 2) 2013.3
v5.0(Rev. 1) 2013.2
v5.0 2013.1

General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP 3GPP Turbo Encoder (TCC) core.
 
Answer Record Title
N/A N/A 


Known and Resolved Issues
The following table provides known issues for the LogiCORE IP 3GPP Turbo Encoder (TCC) core, starting with v5.0, initially released in Vivado 2013.1.
 
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
 
Answer Record Title Version Found Version Resolved
(Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error:
Failed to find design work <Core name>? 		v4.1 v5.0


Revision History:
03/23/2015 - Added v5.0(Rev. 1), v5.0(Rev. 2), v5.0(Rev. 3), v5.0(Rev. 4), v5.0(Rev. 5) and v5.0(Rev. 6) to Version Table
04/03/2013 - Initial Release
AR# 54472
日期 04/01/2015
状态 Active
Type 版本说明
Tools
  • Vivado Design Suite - 2013.1
IP
  • Turbo Convolutional Code Decoder, CDMA2000/3GPP2