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AR# 54477

LogiCORE IP G.709 FEC Encoder/Decoder - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the LogiCORE IP G.709 FEC Encoder/Decoder core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP G.709 FEC Encoder/Decoder core IP Page:


General Information

Supported Devices can be found in the following three locations:

  • LogiCORE IP G.709 FEC Encoder/Decoder core Product Guide
  • Open the Vivado tool -> IP Catalog, right-click on an IP and select "Compatible Families"

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Vivado Tools
v2.1(Rev. 5) 2015.1
v2.1(Rev. 4) 2014.4
v2.1(Rev. 3) 2014.3
v2.1(Rev. 2) 2014.2
v2.1(Rev. 1) 2014.1
v2.1 2013.4
v2.0 (Rev. 2) 2013.3
v2.0 (Rev. 1) 2013.2
v2.0 2013.1

Table 2 provides answer records for general guidance when using the LogiCORE IP G.709 FEC Encoder/Decoder core.

Table 2: General Guidance

Answer Record Title

Known and Resolved Issues

The following table provides known issues for the LogiCORE IP G.709 FEC Encoder/Decoder core, starting with v6.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version
(Xilinx Answer 64600) A setup timing violation can occur if Encoder implementation is set to BALANCED or DSP BIAS v2.1 (Rev. 5) N/A
(Xilinx Answer 59744) Behavioral simulation using Synopsys VCS simulator can give incorrect results v2.1 (Rev. 1) N/A
(Xilinx Answer 57929) Why does the core output incorrect data with 2013.3 Vivado Simulator? v2.0 (Rev. 2) N/A

Revision History

05/19/2015 - Added v2.1(Rev. 2), v2.1(Rev. 3), v2.1(Rev. 4), v2.1(Rev. 5) to Version Table and (Xilinx Answer 64600)
03/17/2014 - Added (Xilinx Answer 59744)
10/11/2013 - Added (Xilinx Answer 57929)
04/03/2013 - Initial release



AR# 54477
日期 05/28/2015
状态 Active
Type 版本说明
  • Vivado Design Suite - 2013.1