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  3. AR# 54481: IP Release Notes and Known Issues for LogiCORE IP 3GPP LTE DL Channel Encoder core for Vivado 2013.1 and newer tool versions

AR# 54481

IP Release Notes and Known Issues for LogiCORE IP 3GPP LTE DL Channel Encoder core for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP 3GPP LTE DL Channel Encoder core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP 3GPP LTE DL Channel Encoder core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/do-di-chenc-lte.html

解决方案

General Information

Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Core Version Vivado Tools Version
v3.0 2013.1

General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP 3GPP LTE DL Channel Encoder core.
Answer Record Title
N/A N/A 


Known and Resolved Issues
The following table provides known issues for the LogiCORE IP 3GPP LTE DL Channel Encoder core, starting with v3.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Answer Record Title Version Found Version Resolved
(Xilinx Answer 55057) LTE DL Channel Encoder v3.0 in 2013.1 fails to xsim in testbench (VHDL or Verilog):"Can not
find design unit work.tb_lte_dl_channel_encoder_v3_0_0 in library work"		 v3.0 N/A 
(Xilinx Answer 55061) WARNING issued: [IP_Flow 19-1037] No method available to update the model parameter
'c_mem_init_prefix' during IP Customization in Vivado GUI		 v3.0 N/A 
(Xilinx Answer 55062) v2.2 core designs are failing in simulations "# ** Failure: ERROR : CCH output data fail
Compare Mismatch" 		v2.2 v3.0 
(Xilinx Answer 36670) Why do I receive packet errors when I use the ICH channel encoder? v2.1 N/A
(Xilinx Answer 35766) Why do I receive simulation errors when I use the DCI formats less than 17 bits as outlined
in the LTE standard 36.212 v9.0 ?		 v2.0 N/A


Revision History:
04/03/2013 - Initial Release

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35766 LogiCORE IP LTE DL Channel Encoder v2.1 - Why do I receive simulation errors when I use the DCI formats less than 17 bits as outlined in the LTE standard 36.212 v9.0 ? N/A N/A
36670 LogiCORE IP LTE DL Channel Encoder v2.1 - Why do I receive packet errors when I use the ICH channel encoder? N/A N/A
AR# 54481
日期 11/11/2014
状态 Active
Type 版本说明
Tools
  • Vivado Design Suite - 2013.1
IP
  • 3GPP LTE DL Channel Encoder