Core Version | Vivado Tools Version |
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v3.0 | 2013.1 |
Answer Record | Title |
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N/A | N/A |
Answer Record | Title | Version Found | Version Resolved |
---|---|---|---|
(Xilinx Answer 55057) | LTE DL Channel Encoder v3.0 in 2013.1 fails to xsim in testbench (VHDL or Verilog):"Can not find design unit work.tb_lte_dl_channel_encoder_v3_0_0 in library work" |
v3.0 | N/A |
(Xilinx Answer 55061) | WARNING issued: [IP_Flow 19-1037] No method available to update the model parameter 'c_mem_init_prefix' during IP Customization in Vivado GUI |
v3.0 | N/A |
(Xilinx Answer 55062) | v2.2 core designs are failing in simulations "# ** Failure: ERROR : CCH output data fail Compare Mismatch" |
v2.2 | v3.0 |
(Xilinx Answer 36670) | Why do I receive packet errors when I use the ICH channel encoder? | v2.1 | N/A |
(Xilinx Answer 35766) | Why do I receive simulation errors when I use the DCI formats less than 17 bits as outlined in the LTE standard 36.212 v9.0 ? |
v2.0 | N/A |
AR# 54481 | |
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日期 | 11/11/2014 |
状态 | Active |
Type | 版本说明 |
Tools | |
IP |